Indeed. For instance, dopants can diffuse and metals can intermix with silicon (silicide formation), both degrade device performance. Solder and packages melt before any of this happens.
It is easy to melt the semiconductor in a semiconductor device long before the solder or package materials are melted.
Above a certain temperature threshold, the electrical resistance of semiconductors drops exponentially with temperature, which is why NTC (negative thermal coefficient) thermistors are made of semiconductor materials.
This causes a positive feedback loop that increases the current very quickly and concentrates it through a narrow channel through the semiconductor (so the current density can be extremely high even when the total current is still low), which can easily reach 1500 Celsius degrees, melting the silicon, while the temperature of the package and of the solder remains very low (because the time is too short for the temperature to propagate outwards from the melted silicon channel).
Sure. I'm currently in the 1st year of a master's in nanotechnology. I'm taking courses in quantum physics, semiconductor physics, semiconductor devices and materials physics.
The semiconductor devices course follows Simon Sze's book almost 1:1. I've found Neamen's "Semiconductor Physics and Devices" and Kasap's "Principles of Electronic Materials and Devices" also excellent for additional explanations.
I have been using this for the past few weeks for my thesis in Emacs & VS Code and have loved it! Thank you so much. Writing in a design suite was a really annoying process.
In the scope of my thesis I have to generate a lot of documentation, and I've been looking into parsers whose AST I can use to help automatically generate this. Would this be possible with vhdl_lang, if comments have been added? I currently have a Python script that regexes its way through with a lot of edge cases, but this is not a reliable way of doing it if I want to add more features.
It depends on what you mean by possible. The vhdl_lang crate solves many hard problems required to do document generation such as parsing, disambiguation and connecting references. It solves it in a much more complete and better way then a regex ever could.
So vhdl_lang is a good base for a document generator but it does not implement one today. My hope with this project was to create a generic VHDL language backend that others could build tools upon instead of reinventing the wheel. I myself have focused on the language server and core library itself and not on document generation.
