Assembler optimization is starting to sound like the ASIC tooling I've been reading about. That's exciting given what's been accomplished with that. :)
I'm not sure what your background is or how much you know about this stuff. Unlike software, almost every aspect of the tooling for hardware is Mega-HARD. Also, I collected a ton of shit on that this year in hopes academics or FOSS types will make OSS alternatives to Big Three. So, here's some intro and example links for you to go through to get an idea of processes and techniques involved. Only then, if you're still committed to learning, will I try to organize and send you some links on specific techniques for achieving them.
Note: I was going to post a custom flow w/ example of MIPS processor but damned thing is totally gone from Google and DuckDuckGo. And my filesharing service is down lol. Put an email address, public or disposable, in your profile then I'll send it to you manually. Or just email the address in my profile with your HN name in subject or body. It's too good to pass up. Do read the two intro's first so you appreciate the work that level requires.
I've finished reading the links. The first one was great. Thanks, I learnt something. It's not my field, but I'm vaguely familiar with the workflow, having friends who design ASICs, work at Xilinx, etc. I've encountered some algorithms in advanced compiler texts.
But what I was specifically curious about was applications of stochastic optimization to EDA workflow. It sounded like you'd seen papers on that topic.
My interest is purely in applications of stochastic optimization. I'm not about to jump into EDA.
Ok, now that I know your focus, I basically just used my fast googling technique and searched through recent archives to see if anything popped up. Here's various things in hardware, software, and architecture benefiting from SO to learn from or improve on in your own work.
Note: This does not do stochastic I don't think but a number of other methods. It's significant because it specifically mentions modern, typically large, designs avoid stochastic optimization for global issues because it's cost-prohibitive compared to geometric methods. That might have significant implications outside EDA, too. Might only be good for local optimizations that are tied together some other way.
Assembler optimization is starting to sound like the ASIC tooling I've been reading about. That's exciting given what's been accomplished with that. :)