Sometimes I like to see what I can figure out in 5 minutes without help or using easy search terms. Keep my Google Fu sharp. Clicking on your name would've been way too easy. Although, I probably should've looked just in case before I asked haha.
Anyway, nice to run into you. I remember your writings were some inspiration in my work on an embedded, efficient 4GL. I no longer had the tool or even remember what I read but your writings factored into it a bit I know. So, thanks for that I guess is all I can say there. :)
Btw, I recently discovered the 1802 in my high assurance and anti-subversion research in hardware. That foray was interested in chips that demonstrated extreme reliability and longevity. I looked into spaceflight given overlap in requirements. Discovered it. The Intersil datasheet had amazing amount of info compared to most chips with some impressive claims about what it could handle.
Since you had to study it, do you think it's worth using on an older process node for high-reliability today? Anything good about it you remember that's worth copying today? Or one of the bigger headaches of your career? I'm just curious as verifiable designs will likely require inspectable fabs... which require tiny CPU's. Means I can't overlook any old wisdom from a time with similar constraints.
I liked the 1802 a lot. Nice orthogonal architecture, lots of registers, made writing the emulator a snap. The only problem with it was that it was dog-slow even in its day: 8 clock cycles per machine instruction. I think you could do better today with a modern FPGA.
I'm doing some work on secure hardware (and software) myself. Would love to compare notes. I sent you an email.
" Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations."
Max clock is 3.6MHz. So, better than 8 clock cycles but still dog slow compared to most. 3.6MHz is still very usable in lost of control applications, some logging, and possibly trusted coprocessor if simple function. Speed improvement is a must, though, for the 1802/2.
I remember the 8080 used 3 clock-cycles for a T-cycles, and 2 or three T-cycles for an instruction. It really took years to get one-instruction-per-clock-cycle. Pretty much all modern processors can do that now (or even three or four per)
Thanks as I couldnt recall how average CPU was then. I was writing it off as possibly the safety/reliability sacking the performance a bit. Still wondering about the "noise immunity" feature. Thought all digital gates had that property.
Anyway, nice to run into you. I remember your writings were some inspiration in my work on an embedded, efficient 4GL. I no longer had the tool or even remember what I read but your writings factored into it a bit I know. So, thanks for that I guess is all I can say there. :)
Btw, I recently discovered the 1802 in my high assurance and anti-subversion research in hardware. That foray was interested in chips that demonstrated extreme reliability and longevity. I looked into spaceflight given overlap in requirements. Discovered it. The Intersil datasheet had amazing amount of info compared to most chips with some impressive claims about what it could handle.
Since you had to study it, do you think it's worth using on an older process node for high-reliability today? Anything good about it you remember that's worth copying today? Or one of the bigger headaches of your career? I'm just curious as verifiable designs will likely require inspectable fabs... which require tiny CPU's. Means I can't overlook any old wisdom from a time with similar constraints.