> If you wanted your program to perform well, you'd have to write C that was, more or less, a translation of assembly that you'd constructed in your head first.
Maybe in really old compilers
> You don't write programs with it, you describe hardware with it
Which is fair enough, but it seems the "hardware description" pretends to be of a higher-level than it really is.
If you need the user to describe gates and flip-flops and how they connect then make them describe this.
> You're talking about RTL, which is exactly what these languages output.
If VHDL/Verilog would output RTL, you could easily analyze it just as you analyze assembly output of your favorite compiler. Unluckily the output is some proprietary bitstream for the FPGA.
Just as a software compilation flow is devided into preprocessing, compilation, assembly, and linking, a HDL flow is divided into synthesis, mapping, place and route, timing analysis and bitstream generation. RTL is the output of the synthesis stage and is readily available to the designer, typically both as code and as a graphical schematic.
Maybe in really old compilers
> You don't write programs with it, you describe hardware with it
Which is fair enough, but it seems the "hardware description" pretends to be of a higher-level than it really is.
If you need the user to describe gates and flip-flops and how they connect then make them describe this.