That's the firmware setting that disables the hack that hides NVMe devices behind the chipset's AHCI controller. Aside from making it possible for standards-compliant NVMe drivers to function as expected, not lying to the OS about the hardware topology also allows the OS to access the PCI configuration space (allowing for eg. ASPM support) and not unnecessarily share interrupts between two entirely separate devices.
If it served a useful purpose in the first place, yes. And if it were properly documented and didn't cripple certain areas of functionality (and probably hurt performance a bit, but I don't yet have a system to measure this with).
