You cannot do this kind of error correction it like ECC checking in the CPU because it would require multiple clocks or too many pins.
You cannot do this kind of error correction across multiple DRAM chips on board because it would require too many pins.
But you could do this kind of error correction on-chip because you could just read 1024 bits (or more) in parallel from multiple areas (or even mutliple stacked silicon slices).
One problem, however, is that each small read would induce a high energy cost due to the many bits fed into the extensive error correction circuitry. While it shouldn't be a problem for consecutive reads, random-access would indeed lead to a high power consumption which in most cases would not be acceptable.
You cannot do this kind of error correction it like ECC checking in the CPU because it would require multiple clocks or too many pins.
You cannot do this kind of error correction across multiple DRAM chips on board because it would require too many pins.
But you could do this kind of error correction on-chip because you could just read 1024 bits (or more) in parallel from multiple areas (or even mutliple stacked silicon slices).
One problem, however, is that each small read would induce a high energy cost due to the many bits fed into the extensive error correction circuitry. While it shouldn't be a problem for consecutive reads, random-access would indeed lead to a high power consumption which in most cases would not be acceptable.