VHDL compared to Verilog and SystemVerilog has much smaller user base and is less well supported by tools. And HW designers are hugely conservative when it comes to languages.
A raeson for this is that we have so many tools and the subset we can use the the GCD of all parsers in all tools.
Linter, EC-checker, simulator (at least one, often more than one), planner, synthesis/build tool, integration tool etc.
The synthesis subset of Verilog 2001 and 2005 are as far as I have seen accepted by virtually all tools. I tend to err on the side of caution and use Verilog 2001.
A raeson for this is that we have so many tools and the subset we can use the the GCD of all parsers in all tools.
Linter, EC-checker, simulator (at least one, often more than one), planner, synthesis/build tool, integration tool etc.
The synthesis subset of Verilog 2001 and 2005 are as far as I have seen accepted by virtually all tools. I tend to err on the side of caution and use Verilog 2001.