A keeper, if nothing else (and there's much more) for the ultra-clear chart of three stages of CPU performance, 1978-2006, on page 4.
The Azul Systems site mentions their own 54-core CPU ( http://www.azulsystems.com/technology/vega ), but there does not seem to be much publicly available about the architecture. I was wondering if it was a Sparc derivative (the PDF also mentions Sun's Niagara for Chip Multi Threading). They had a legal tiff with Sun in 2005-2007 ...
P.S. Coincidentally, one of the presentation's references for further reading is the 2007 monograph by Ulrich Drepper also gracing the frontpage of HN today at http://news.ycombinator.com/item?id=1394346
Thanks. I just found out there's a text abstract one can click to expand ... Snippets:
[...] The cores are our own design; simple 3-address RISCs with read- & write-barriers to support GC, hardware transactional memory, zero-cost high-rez profiling, and some more modest Java-specific tweaks. [...] history with designing our own chips (1st silicon back from the fab had problems like the bits in the odd-numbered registers bleeding into the even-numbered registers)[...]
The Azul Systems site mentions their own 54-core CPU ( http://www.azulsystems.com/technology/vega ), but there does not seem to be much publicly available about the architecture. I was wondering if it was a Sparc derivative (the PDF also mentions Sun's Niagara for Chip Multi Threading). They had a legal tiff with Sun in 2005-2007 ...
Couple of links: http://en.wikipedia.org/wiki/Azul_Systems , http://www.taranfx.com/boost-java-performance-5x-times-hardw...
P.S. Coincidentally, one of the presentation's references for further reading is the 2007 monograph by Ulrich Drepper also gracing the frontpage of HN today at http://news.ycombinator.com/item?id=1394346