I figured out the shift-register circuit, but decided to write up the digital logic separately since the blog post was already very long. It's a 32-stage nonlinear feedback shift register. The sequence repeats after 56883 steps, which is a lot less than 2^32, so it seems to me they aren't making good use of the stages. The output takes a while to get going: it is high for 30 clocks and low for 31 locks before oscillating. I don't like to criticize, but it doesn't really look like a good design to me. The digital mixer is also pointlessly complex.
With a linear feedback shift register, the input is the XOR of some stage outputs. (XOR is linear when considered mathematically since it's basically bitwise addition.) If you use other logic functions, then it's nonlinear. The 76477 uses a combination of XOR and NAND, making it nonlinear. The disadvantage of a linear feedback shift register is it can get stuck at all zeros. But the 76477's shift register gets set by the inhibit line, so it couldn't get stuck. So I really don't know why they used a nonlinear circuit. As far as I can tell, it just makes the performance worse.
They could have made the chip a lot smaller (= cheaper to produce). For the period they actually achieved, they could have gotten away with a 16-bit LFSR, requiring half the die area for that function (which looks like it was quite significant).
16 isn't a good size according to the Rosenberg paper (http://www.cs.miami.edu/~burt/learning/Csc609.022/random_num...) but 15 and 17 are sizes you could program an ATtiny45 to generate if you just wanted that quality of noise. I'm going to be real interested in trying out the actual noise-generator logic in the follow-up article to see if I can hear any useful tonal difference. Maybe they were just frustrated by hardware that kept drifting into the forbidden state and brute-forced it until it couldn't; I've had that happen with PRNGs I built with series-4000 CMOS logic and xgates. Stay tuned, I guess.
