I learned from MIT's 6.004. They provide infrastructure for you to build a simple core from gates for a RISC ISA in their own test environment. Their materials should be online (or available via OCW).(E.g., https://www.youtube.com/watch?v=CvfifZsmpQ4).
Once you understand how to build a core, frankly the more daunting part is how to interface with the core. How do you load a program into its memory? How do you see what it is doing? How do you know if it finished running or if it crashed?
You may find luck following along with FPGA tutorials (maybe take a look at the Pynq board?) that teach you how to implement a design, put it on the board, and talk to it. Once you understand how to use your FPGA and how to interface with your designs, changing the design to a simple RISC-V core will be more tractable.
You could try and check out picorv32 or riscv-sodor to see two examples of "simple" RISC-V cores that you can build, simulate on your computer, and watch them execute programs you wrote. But man the "magic" behind the test harnesses can be super opaque.
Once you understand how to build a core, frankly the more daunting part is how to interface with the core. How do you load a program into its memory? How do you see what it is doing? How do you know if it finished running or if it crashed?
You may find luck following along with FPGA tutorials (maybe take a look at the Pynq board?) that teach you how to implement a design, put it on the board, and talk to it. Once you understand how to use your FPGA and how to interface with your designs, changing the design to a simple RISC-V core will be more tractable.
You could try and check out picorv32 or riscv-sodor to see two examples of "simple" RISC-V cores that you can build, simulate on your computer, and watch them execute programs you wrote. But man the "magic" behind the test harnesses can be super opaque.