Hacker Newsnew | past | comments | ask | show | jobs | submitlogin

Yeh I realised afterwards that at these high clock speeds maybe they do need some extra cycles to do the correction. I don't see why you must do it in hardware to avoid timing side-channels. You just need to provide a constant latency i.e. The cpu ucode does some nops when correction is not necessary.


I mean, as long as your ECC is built directly into the silicon


In that case you need to do the exact opposite i.e. avoid the obvious optimisation of returning data early if no correction is required.




Consider applying for YC's Summer 2026 batch! Applications are open till May 4

Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: