It is pretty common to use DRAM with an FPGA to manipulate large amounts of data. I clarified my essay: "eg. to store or manipulate large quantities of timestamps or events data that do not fit in SRAM".
Changed to "artifacts of the FPGA" (as in "the FPGA platform", which includes the crystal oscillator, DRAM, and everything else that might be responsible).
I understand you don't want to change because it does invalidate a big portion of your article. But by dancing around the problem, instead of addressing it, you did weaken the trustworthiness of your article, and make it sound more of a witch hunt (read: chasing idea without much evidence).
You have two points that I think are reasonable to raise: (1) is there a mistake (intentional or not) in the assumed margin of error in the measuring equipment? (2) is the DRAM caching behavior taken into consideration? Neither of these two points have anything to do with FPGA per se. Now by including the enchilada word "FPGA platform" into the fray (whereas it was clearly not the intention at the beginning), I feel like you are making things up as you go, which is unfortunate since part of your argument is valid.
It is pretty common to use DRAM with an FPGA to manipulate large amounts of data
True, but your essay confuses acquisition with storage. As a rule, by the time the data is stuffed into a DRAM somewhere, it's already been timestamped. If you're right, and it hasn't been, then, yep, that's (a) problem.
