The metal wire connects the input to the two gates. The PMOS (upper) transistor turns on if the input is low; it connects the output (right) to the high voltage (left). The NMOS (lower) transistor turns on if the input is high; it connects the output to the low voltage. Each transistor has a contact (via) that connects the transistor to the gate's output. Thus, working together the two transistors implement an inverter. The power connections to the transistor aren't shown in the diagram; they are off to the left.
As for the shapes, they are basically created as a consequence of the routing. The gate is the important part; it needs to be a rectangle with specific dimensions (based on the circuit). The rest of the transistor can meander as needed. Because there's only one metal layer, a lot of routing needs to be done through the silicon.
The cross-section diagrams earlier in the article might help.
>"The power connections to the transistor aren't shown in the diagram; they are off to the left."
What does the power connection to the transistors look like? I guess it's another two vias, one into the source side and one into the drain side that connect to the power rail? I'm guessing there's metal in the source and drain similar to the gate where these terminate?
>"The gate is the important part; it needs to be a rectangle with specific dimensions (based on the circuit)."
Could you elaborate on why it needs to be rectangle? Are the specific dimension based on resistance needed in the circuit then?
> What does the power connection to the transistors look like?
With one layer of metal, power wiring is tricky. You need to get power and ground to all parts of the chip in the metal layer, without crossing. (You can use the silicon layer to cross if necessary, but this adds resistance so is avoided if possible.) So you end up with power wiring either meandering all over the chip, or an interdigitated tree-like structure for power and ground.
A via connects the power (or ground) metal wiring to the silicon layer. This silicon will often feed several nearby transistors, rather than one via per transistor.
(Hopefully this makes sense.)
> Could you elaborate on why it needs to be rectangle?
I guess you could have non-rectangular gates, but it's not something I see. The gate is where a metal line crosses a silicon region, so you naturally end up with a rectangle. The current is proportional to the width::length ratio of the gate, so the dimensions are important. (And one dimension is normally constrained by the minimum feature size.)
>"A via connects the power (or ground) metal wiring to the silicon layer."
Would those vias be what's labeled here in this diagram as "metal contact" above both the source and drain then? Is it just for simplicity sake that they show it having a one to one relationship?
Yes. (I can never remember the official difference between contacts and vias, so I use them interchangeably.) However, an important thing on a chip is that you don't need to connect the source and/or drain to the metal layer; you can connect it to something else through the silicon. You can extend the source or drain (i.e. diffused silicon) until it runs into another transistor's source or drain. There's not really any difference between silicon doped for a source/drain and silicon doped for wiring. This is especially useful when you have a single layer of metal wiring, since you can cross signals by using metal wiring for one and silicon wiring for the other.
As for the shapes, they are basically created as a consequence of the routing. The gate is the important part; it needs to be a rectangle with specific dimensions (based on the circuit). The rest of the transistor can meander as needed. Because there's only one metal layer, a lot of routing needs to be done through the silicon.
The cross-section diagrams earlier in the article might help.