I habe a few lying about. My fun project is to implement a usb CCID (smartcard) device to create a pkcs11comiant HSM from scratch (FYI the ESA dis this on MAX10s for one of their satellites or probes). Assuming you dev environment is not compromised. USB 1.1 and USB 2.0 have free/OSS IP cores.
Personally, I do not see point in implementing a softcore
Cpu unless design absolutely requires it.
Separately, FPGA makers has shifted focus a bit from facilitating hardware design to providing coprocessors/accel cards.
Personally, I do not see point in implementing a softcore Cpu unless design absolutely requires it.
Separately, FPGA makers has shifted focus a bit from facilitating hardware design to providing coprocessors/accel cards.