I thought that Intel AVX10 was limited to vector instructions, but they are re-arranging the instruction set and doubling general-purpose CPU registers.
And adding lots of conditional instructions, so that common loop patterns can be mapped onto a conditional instruction, rather than written out as a branch to another code path.
This architecture extension is called Intel APX, referenced by the AVX10 extension, but I don't recall hearing about it before.
APX will not need any additional hardware space, as they are carving these 64-but registers out of the deprecated MPX registers.
Wait, what?
I thought that Intel AVX10 was limited to vector instructions, but they are re-arranging the instruction set and doubling general-purpose CPU registers.
And adding lots of conditional instructions, so that common loop patterns can be mapped onto a conditional instruction, rather than written out as a branch to another code path.
This architecture extension is called Intel APX, referenced by the AVX10 extension, but I don't recall hearing about it before.
APX will not need any additional hardware space, as they are carving these 64-but registers out of the deprecated MPX registers.
Memory Protection Extension https://en.m.wikipedia.org/wiki/Intel_MPX