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sudosysgen
on April 25, 2024
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More on x86 – The Chip Letter
The L1 latency constraint is a size constraint - if you increase the L1 size, you simply cannot avoid increasing L1 latency.
gpderetta
on April 25, 2024
[–]
That's what I meant: for performance considerations, L1 latency must be limited to single digit cycles on a general purpose CPU, hence L1 size is capped.
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