Do you consider 800+mm2 slabs of 3nm of silicon still toy size? Because there's a very high chance that those were written in Verilog, and I've never had to chase sim vs synthesis mismatches.
> Verilog gives you enough rope.
Yes. If you don't know what you're doing and don't follow the industry standard practises.
Do you consider 800+mm2 slabs of 3nm of silicon still toy size? Because there's a very high chance that those were written in Verilog, and I've never had to chase sim vs synthesis mismatches.
> Verilog gives you enough rope.
Yes. If you don't know what you're doing and don't follow the industry standard practises.