> As an early proof of concept, Kimi K3 designed a chip to serve a nano model built on its own architecture. In a single 48-hour autonomous run, K3 built, optimized, and verified the chip using open-source EDA tools on the Nangate 45nm library. Within 4 mm², the chip closes timing at 100 MHz and sustains over 8,700 tokens/s decode throughput in simulation, packing 1.46M standard cells, 0.277 MB of SRAM, and an INT4 MAC array with fused dequantization. A chip built by a model, for a model, reflects K3's long-horizon agentic capabilities.
I had a thought a while back: sell large local models burned onto fused compute / ROM chips. Like cartridges for old game consoles. Slot (or probably plug into USB-C) and go.
It’s an ASIC with the model wired into it so it’s very low power and fast.
I’d buy these. Say $100 for a frontier class model. Maybe more.
Taalas is developing this, but not for Frontier class models. I hope that if we can least get the easy 80% of work done on that sort of hardware, we can greatly reduce the demand for GPUs, HBM and energy to some extent.
There is an amount of brute forcing that becomes possible at those speeds that I think could even take us beyond 80%. If we could have Qwen3.6-27B running at 15k t/s, run 100 attempts concurrently, select top-K solutions and synthesize a final result from them.
There was a paper a while back that showed top-K selection like that with tiny models was able to reliably solve some 1M-step Tower of Hanoi when no frontier model could. Very big level up in capability just from horizontally scaling compute.
To extend this metaphor or the "million monkeys typing at a million keyboards", it occurs to me that if you can just slightly increase the intelligence of each sub-agent by a tiny amount, the overall end product can shoot up in quality tremendously.
If I can make my small fast AI model just a tiny, tiny bit more capable, and still run 100 of them or 1000 and run an evaluation model on top of that, the overall system capability will scale quickly with tiny increases in base model intelligence.
But some (Meta, Anthropic) suggested that optimizing and extending the "<think>" process can produce extra value. (I do not know if that requires an improved underlying architecture - frontier models architectures are sometimes not public.)
They've unfortunately been radio silent since their release, and aren't active on socials at all. I've tried to contact them for updates / api usage, but haven't heard anything back.
Looking at their career page it looks like they do not care that much about PR at the moment... considering that they have a live chat with 14000t/s via Llama 3.1 8B[0] i don't really think they need to do PR either.
So i guess maybe they currently try to solve a very hard problem with a small focused group before scaling or they are dysfunctional.
Also Llama 3.1 8B is a dense model AFAIK and they are fast by nature.
As there are not a lot of dense models these days i could imagine that they try to optimise for MOE models.
In Gibson’s Neuromancer AIs burned onto chips were literally discussed and called “ROM constructs.” In that case some of them were images of human minds but with no persistent state or memory.
So basically a static model version of consciousness uploading.
You’re expecting the wrong thing. The demo demonstrates the insane inference rate of dedicated hardware. Iirc it’s llama 3 or something. Not a very good model by today’s standards. But it runs at 16k tokens per second, an order of magnitude above the competition.
Imagine what’s possible if you had GLM-5.2 turned into a hardware chip like this.
It's a custom 3 bit quant of Llama 3.1 8B and other shortcuts. The quant is not good. Their newer arch switches to standard 4 bit quants, should be far better!
I believes the weights are burned as ROM microcode, but for an effective inference speedup, you do want to burn the architecture (matmuls, activation functions, MoE gates, etc) as well which will differ from model to model.
It's not as simple as a weight swap between identical architectures.
The speed gains are also from not having to route the weights through wiring like with ROM cartridges.
> I’d buy these. Say $100 for a frontier class model. Maybe more.
Sure you would. Running frontier class models on current hardware costs in the order of tens of thousands of dollars. It is more likely that these custom ASICs will be priced competitively with that, and not with Super Mario Bros.
Oh, and energy consumption will be in the same order.
This is a fun idea but they'll be outdated in 6 months and it would take 12 months to develop, build and ship them assuming they can design and manufacture these at superhuman speeds.
Interestingly, you could easily run them from the said old consoles! You'd just need a bit of console code to interface (text input/output) with your fully independent LLM subsystem. Imagine Claude for the NES without Internet?
This would be very compelling. Can anyone share more details on how it would work? Only issue is that you are stuck at a certain point in time but that’s not a huge deal. Even just a good 27b model would be useful.
Talaas have done this with a llama 3 model.
Runs at like, 16k/tokens a second oror something obscene. Very little power draw too.
Doesn’t need hbm or lots of memory, because the hardware can just forward the data straight to the next layer and you don’t need to round trip through memory.
They claim to be working on an approach to make the underlying hardware a bit more reusable between models.
Yeah, if you have a fixed llm topology, you can just effectively burns 2 top layers of the chip as Rom (model weights) - which has a per area density even better than dram - so it’s just attention and kv streaming that is hbm to sram transfer.
Most big model weights will not fit a single reticle sized chip - so you’d have prob 30 different chips to split the model .
And you’d need super fast chip to chip comms for the all-reduce and similar.
So scaling to 1T models is hard - and a long lead time - but can be very power efficient.
> “In the current generation, our density is 8 billion parameters on the hard wired part of the chip., plus the SRAM to allow us to do KV caches, adaptations like fine tuning, and etc. In our next generation, we would have the ability to go up to 20 billion parameters in a chip. Even with trillions of parameters, we’re talking about few tens of chips, which is a very, very small compared to anything else out there on the market today.”
1) the hardest, custom silicon + MCU to manage the USB interface
2) not as hard, shared memory, NPU + MCU to manage inference and USB interface
Theoretically you could do 2 with the right MCU, NPU, and memory combo. You'd stream/DMA the weights from memory into the NPU and then read the results with the MCU. From a user's perspective, it might take the form of an openAI API compatible endpoint that enumerates when they plug the USB device in. There would likely be some host-side software to ease the pain of trying to use a USB device as an HTTP API.
I wonder, if you can run at 8k or 15k t/s, you could in theory run 10 or 20 agents (or more) at the same time and generate hundreds of versions, then just analyze them. Think thinking mode x1000 at least... Would be interesting to see how good it would be
Less impressive than you might think here. I can't imagine how small this model must be if it only has 1.46M cells. Maybe 1M? Probably less. Sure the token/s decode is cool, but this size isn't capable of doing anything. For context: this is a 45nm process.
In comparison, Taalas' implementation (which everyone likes to talk about) is in 6nm, is 815mm^2, and only serves a 8B parameter ~4-bit quant model.
So, 815mm^2 in 6nm is roughly equivalent to ~6112mm^2 in 45nm. If we assume everything scales exactly the same, 4mm^2 would be ~1500x smaller. 1500x smaller means at best we're talking about a ~5M parameter model. I don't know how you'd get a 5M param model (with multiple bits) in 1.46M transistors.
groq did an ASIC for llama and now for nvidia. Their cloud service is fast.
> NVIDIA Groq 3 LPU Inference Accelerator
> The NVIDIA Groq 3 LPU is the next generation of Groq’s innovative language processing unit. Each LPX rack features 256 interconnected LPU accelerators that, together with the NVIDIA Vera Rubin platform, supercharge inference. Each LPU accelerator delivers 500 megabytes (MB) of SRAM, 150 terabytes per second (TB/s) of SRAM bandwidth, and 2.5 TB/s scale-up bandwidth.
The bottleneck is physical stuff: chip fab is still a whoooooole beast. Doesn't matter too much if AI can design chips, the lead times are still in the years. Assuming you use existing fabs. If you need new fabs, now it's decades.
And there's not too too much that can be done here. Robotics, sure, but robotics are very behind AI because physical space is just hard. We can't, right now, just spin up like 1000 robots and build a fab.
Geoffrey Hinton pointed out that exponential growth can be hard to see in the near term (2-3 years) because that part is a bit within predictions, but, it's the exponential part which means 5+ years out is totally unpredictable.
Lol even few people here are grappling with the exponential unfolding before us. There are so few deeply thought through takes of where we’re going and why there are extremely concerning issues.
This edition of the Fields Medal (btw, two Chinese mathematicians also received this honor) is basically certain to be the last purely human Fields Medal.
I cannot imagine how much context window it needs for this. I am struggling with local AI in Pi to even get small (500-1000 lines of code) programs written without overrunning a 220k context. Doing all this EDA design and testing must surely require millions of tokens of context window right? Maybe they just do a far better job of architecting the work and sub-tasking it to sub-agents, each with their own context, to keep the primary context window from overfilling.
> As an early proof of concept, Kimi K3 designed a chip to serve a nano model built on its own architecture. In a single 48-hour autonomous run, K3 built, optimized, and verified the chip using open-source EDA tools on the Nangate 45nm library. Within 4 mm², the chip closes timing at 100 MHz and sustains over 8,700 tokens/s decode throughput in simulation, packing 1.46M standard cells, 0.277 MB of SRAM, and an INT4 MAC array with fused dequantization. A chip built by a model, for a model, reflects K3's long-horizon agentic capabilities.
Absolutely wild.