Hacker Newsnew | past | comments | ask | show | jobs | submitlogin

Do you have any more details or links to articles about this that I could read?


I don't know of specific articles but I suspect you'd find some on Intels website.

In short, in current CPU generations (x86_64 is what I work with) the PCIe controller is on the CPU die so if you have multiple CPUs you have multiple PCIe controllers and each of them control different PCIe sockets. You need to consult your motherboard to know which sockets will go with which CPU.

If an interrupt comes from a PCIe card it will trigger on the CPU that is attached to it, if the process that needs to handle the data is on the other CPU you need to transfer the data and the cache to the second CPU, it's a small effect but if you really care about performance and want to squeeze every nanosecond of latency on your work you should care about this.

You should start by considering in which slot to stick which card and if you have a multiple of PCIe cards you really want to balance them out.


Not just latency, with 10 gig Ethernet doing udp/multicast it can be a pretty huge effect throughput wise (TCP with a card that supports offloading not quite so much).


The throughput would be affected by the latency increase. I believe the QPI link between the processors has enough bandwidth so the extra latency to transfer the data between the processors and the reduced performance due to cache switch-overs would be the source of the reduced throughput.


The only relevant piece I could find quickly was the Mellanox performance tuning guide: http://www.mellanox.com/related-docs/prod_software/Performan...

It's also useful for any other PCIe card, sans the IB specific parts.




Consider applying for YC's Fall 2026 batch! Applications are open till July 27.

Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: