Race logic with pulses, it's a descent of systolic arrays. There is less of an a... | Hacker News

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skyberrys 48 days ago | parent | context | favorite | on: AI Chip Architectures

Race logic with pulses, it's a descent of systolic arrays. There is less of an array shape and more about time.

whaleofatw2022 48 days ago | [–]

Dumb question, wouldn't node size impact the logic latency itself on some level?

skyberrys 48 days ago | | [–]

Yes smaller nodes give lower power operation with faster transistor switching speeds. You can also underpower a node to intentionally cause slower transistor switching speeds.

brcmthrowaway 48 days ago | [–]

Where can I find the whitepaper?

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