Surely yield is very much a function of the size of the device in question and its tolerance for defects. I don’t think it makes sense for a technology to have a theoretical maximum yield that’s a constant number unless it somehow destroys entire wafers with highish probability.
You can normalise by surface area, which makes defects rate comparable across processes. At least to a first order approximation, keeping all other parameters constant, bigger chips are more likely to have a defect because they have larger surface areas.
If a process has a defect rate of x, the probability of a die having a defect is A*x. The limit is then the defect rate for a die with the surface area of a transistor, you cannot really get any better than this. But that’s not very useful if you want to extrapolate what the defect rate would be on an improved or cheaper process.
