Hacker Newsnew | past | comments | ask | show | jobs | submitlogin

Reading the article, I see no reason why there should be any major performance issues inherent to RISC-V. Lack of an ecosystem looks like the issue, at least initially. But a $1m licensing fee for a CPU with an established ecosystem is an issue too...


The reason the chips will be slower in practice is because they are produced in small batches, and need to be produced by smaller fabs and by extension much older process. MIPS is routinely produced at 95nm still.


We at lowRISC intend to produce in volume at 40nm or 28nm. http://www.lowrisc.org/


Looks really interesting. Where are you guys based? Cambridge, UK I'm guessing?


Yes, the core team is based in Cambridge, UK. However we do intend to be a truly open-source project, with an open and distributed development process which would involve arbitrarily geographically distributed third-party contributors.


That's truly great to hear!


MOSIS offers multi-project wafer (MPW) runs at 28nm from GlobalFoundries.

https://www.mosis.com/products


Yes, and the fact that most of the performance comes from the micro-architecture.

CPU design is all about the tradeoff between size, complexity, speed and power consumption.

New RISC architectures tend to start on the low-end of the scale (clean architecture, short pipeline, small die), and if they are successful, move toward the x86/ugly/big/complex/fast spot.




Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: